The present invention generally relates to phase lock loop circuits and, more particularly, to a multi-phase network circuit providing for spurious-free-fractional N frequency synthesis.
Phase lock loop (PLL) circuits can be used in a variety of applications including frequency demodulation, frequency multiplication and pulse synchronization, to name just a few. PLLs generally have a structure including a phase detector, a proportional-integrated loop filter, a voltage controlled oscillator (VCO) and an optional amplifier. The phase detector continuously generates an output signal that is proportional to the input phase error between the signals present at its inputs. This error signal is transmitted to the proportional-integrated loop filter to perform a proper phase characteristic of the PLL control loop. The output signal of the loop filter controls the VCO.
The VCO operates to convert the input voltage signal into a time derivative phase signal. As such, the VCO acts as an integrator. Consequently, any jitter or unwanted modulation present in the input signal of the VCO will cause a linearly increasing phase error in the VCO output. High frequency component of the VCO input error directly results in output signal error, which can degrade the operation and/or performance of the PLL or a larger system which incorporates or uses the PLL.
Feed-back dividers are generally included into PLL feed-back loop to control output frequency. In case of integer division ratio of the feed-back divider the PLL output frequency step equals to input reference frequency. In other words, to obtain more fine granularity of the output frequency step fractional divider is used.
There are two popular methods of fractional division implementation. The first method assumes implementation of fractional division as averaging a series of integer division. For example if one wants to divide by 5.5 then one division stage will provide division by 5, and the second division stage will provide division by 6, with the average of such stages resulting in division by 5.5. This method unavoidably produces spurious modulations of the VCO output signal, especially for fine fractional division because in this case fractional division produces low-frequency components which pass proportional-integrated loop filter, and produce unwanted modulation at the VCO output.
The second method is fractional N phase interpolation. In fractional N phase interpolation, the VCO of a PLL generates N output signals, each having a different phase relative to the other output signals. An output signal is a superposition of two signals with adjacent phases having a phase located between those two signals phases. This method, however, still suffers from the aforementioned problems associated with non-attenuation of modulation associated with the interpolation procedure.
In addition to single output applications, PLLs are used to generate a plurality of output signals which, in turn, are used to control a plurality of components within a larger system. In those applications where a PLL is used to create multiple output signals having different frequency values, modulation or other unwanted jitter in the input signal will then propagate throughout the multiple phase generation stages of a larger system, thereby resulting in each of the controlled components operating incorrectly.
Thus, there is a need for an improved phase lock loop which negates the effects of input and output signal modulation or jitter, while at the same time providing fractional or multi-frequency versions of the input signal.